Kuncheng Liu
Kuncheng Liu

Kuncheng Liu

Undergraduate @ USTC

Hefei, China

Hello, I'm Kuncheng.

I am currently an undergraduate student at the University of Science and Technology of China (USTC), and a member of the prestigious Huang Kun Talent Class (jointly trained by the Institute of Semiconductors, CAS).

My academic journey has been enriched by visiting research experiences at Harbin Institute of Technology (HIT), Hong Kong University of Science and Technology (HKUST), and the Institute of Microelectronics of the CAS (IMECAS). I am also a recipient of the Outstanding Student Scholarship.

My research interests lie at the intersection of quantum optics and semiconductor device physics. Currently, I am focusing on SiC power devices in Prof. Zheyang Zheng's group at the School of Microelectronics, USTC.

Previously, I worked on integrated photonics under the supervision of Prof. Xifeng Ren at the CAS Quantum Information Laboratory.

Latest News

  • Nov 2025 Setup my new academic website on JD Cloud.
  • Sep 2025 Joined Prof. Zheng's group for SiC research.

Research Experience

SiC Power Devices Characterization

Advisor: Prof. Zheyang Zheng, School of Microelectronics, USTC

Current

Silicon Carbide (SiC) is a wide-bandgap semiconductor material that is revolutionizing the power electronics industry. In this project, I am:

  • Investigating the threshold voltage instability of SiC MOSFETs under high-temperature bias.
  • Using TCAD simulations to model the device physics and validate experimental data.
  • Analyzing the impact of interface traps on device performance.

Integrated Quantum Photonic Chips

Advisor: Prof. Xifeng Ren, CAS Quantum Information Laboratory

Previous

Participated in the design and testing of integrated photonic circuits for quantum information processing. Key contributions included:

  • Assisted in the layout design of optical waveguides using L-Edit.
  • Performed optical coupling experiments to measure transmission efficiency.
  • Studied the generation of entangled photon pairs on silicon-on-insulator platforms.